U.S. Pat. No. 5,877,523 has described a semiconductor memory cell, which is suitable for storing a plurality of bits. In this cell, two separate floating gate electrodes are located at the ends of a channel region above two adjoining LDD regions of source and drain. A control gate electrode is present for driving purposes. Charges can be stored separately in the two floating gate electrodes, in order in this way to alter the relevant programming state of the cell. In a middle part of the channel region there is only the control gate electrode above a dielectric layer on the semiconductor material.
German Patent No. 100 36 911 C2 has disclosed a method for fabricating a multi bit memory cell which has separate parts of a storage layer which are intended for charge trapping and are in each case present at the boundaries between source or drain and the channel region. In this method, a source region and a drain region are formed by the introduction of dopant in a semiconductor body, and a storage layer which is intended to store charge carriers is arranged between boundary layers above these regions; the storage layer may in particular be a nitride, and the boundary layers may in each case be oxide, and the storage layer may be removed with the exception of regions that are located at the boundary between the channel region and the source region and at the boundary between the channel region and the drain region. Therefore, the storage layer is interrupted above a middle part of the channel region. This structure is fabricated by the production of an auxiliary layer which, in the region of the storage layer, has a cut-out, with spacers produced at the flanks of the auxiliary layer. Then, the middle parts of the storage layer are removed between these spacers. Only then is the gate electrode fabricated and patterned.
U.S. Pat. No. 5,714,766 has described a memory component having a transistor structure with source/drain regions, a channel arranged between them and a storage layer structure between the channel and a gate electrode, wherein the storage layer structure comprises upper and lower barrier layers and nanocrystals arranged between them. The document mentions silicon, germanium, silicon-germanium, silicon carbide, gallium arsenide, indium arsenide and other IV, III–V and II–VI semiconductor materials, as well as compound semiconductors formed therefrom, as material for the nanocrystals.
The publication by J. von Borany et al.: “Memory properties of Si+ implanted gate oxides: from MOS capacitors to nvSRAM” in Solid-State Electronics 46, 1729–1737 (2002) describes the properties of memory components in which silicon regions described as nanoclusters have been produced by implantation of Si+ into the gate oxide. The gate electrode is applied direct to a layer of this type.
U.S. Pat. No. 6,335,554 B1 describes a memory cell having a charge trapping layer, which is present above the junctions between LDD regions and the channel region and at the flanks of the gate electrode. Two gate electrodes, which are in each case designed in the form of spacers are present above the charge trapping layer and are connected to the first gate electrode via a top-side conductive layer.